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XC5200 Series Field Programmable Gate Arrays
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Product Specification Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series - Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available Fully Supported by Xilinx Development System - Automatic place and route software - Wide selection of PC and Workstation platforms - Over 100 3rd-party Alliance interfaces - Supported by shrink-wrap Foundation software
Features
* Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 "gates") - Price competitive with Gate Arrays * System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRingTM I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins - Internal 3-state bussing capability - Four dedicated low-skew clock or signal distribution nets * Versatile I/O and Packaging - Innovative VersaRingTM I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals - Programmable output slew-rate control maximizes performance and reduces noise - Zero Flip-Flop hold time for input registers simplifies system timing - Independent Output Enables for external bussing *
Description
The XC5200 Field-Programmable Gate Array Family is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to programmable logic design. The VersaBlockTM logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar Xilinx software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, VHDL, and Verilog HDL synthesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices.
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Table 1: XC5200 Field-Programmable Gate Array Family Members Device Logic Cells Max Logic Gates Typical Gate Range VersaBlock Array CLBs Flip-Flops I/Os TBUFs per Longline XC5202 256 3,000 2,000 - 3,000 8x8 64 256 84 10 XC5204 480 6,000 4,000 - 6,000 10 x 12 120 480 124 14 XC5206 784 10,000 6,000 - 10,000 14 x 14 196 784 148 16 XC5210 1,296 16,000 XC5215 1,936 23,000
10,000 - 16,000 15,000 - 23,000 18 x 18 324 1,296 196 20 22 x 22 484 1,936 244 24
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XC5200 Family Compared to XC4000/SpartanTM and XC3000 Series
For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000/Spartan and XC3000 devices.
Table 2: Xilinx Field-Programmable Gate Array Families Parameter CLB function generators CLB inputs CLB outputs Global buffers User RAM Edge decoders Cascade chain Fast carry logic Internal 3-state Boundary scan Slew-rate control XC5200 Spartan XC4000 XC3000 4 20 12 4 no no yes yes yes yes yes 3 9 4 8 yes no no yes yes yes yes 3 9 4 8 yes yes no yes yes yes yes 2 5 2 2 no no no no yes no yes
Configurable Logic Block (CLB) Resources
Each XC5200 CLB contains four independent 4-input function generators and four registers, which are configured as four independent Logic CellsTM (LCs). The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches. The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions.
XC4000 family: XC5200 devices have no wide edge decoders. Wide decoders are implemented using cascade logic. Although sacrificing speed for some designs, lack of wide edge decoders reduces the die area and hence cost of the XC5200. XC4000/Spartan family: XC5200 dedicated carry logic differs from that of the XC4000/Spartan family in that the sum is generated in an additional function generator in the adjacent column. This design reduces XC5200 die size and hence cost for many applications. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC3000 has no dedicated carry. XC4000/Spartan family: XC5200 lookup tables are optimized for cost and hence cannot implement RAM.
Routing Resources
The XC5200 family provides a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks. The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source. Each XC5200 TBUF can drive up to two horizontal and two vertical Longlines. There are no internal pull-ups for XC5200 Longlines.
Input/Output Block (IOB) Resources
The XC5200 family maintains footprint compatibility with the XC4000 family, but not with the XC3000 family. To minimize cost and maximize the number of I/O per Logic Cell, the XC5200 I/O does not include flip-flops or latches. For high performance paths, the XC5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers. Each XC5200 I/O Pin provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems. Each XC5200 I/O Pin is capable of 8-mA source and sink currents. IEEE 1149.1-type boundary scan is supported in each XC5200 I/O.
Configuration and Readback
The XC5200 supports a new configuration mode called Express mode.
XC4000/Spartan family: The XC5200 family provides a global reset but not a global set.
XC5200 devices use a different configuration process than that of the XC3000 family, but use the same process as the XC4000 and Spartan families.
XC3000 family: Although their configuration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices. XC3000 family: The XC5200 PROGRAM pin is a single-function input pin that overrides all other inputs. The PROGRAM pin does not exist in XC3000.
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XC3000 family: XC5200 devices support an additional programming mode: Peripheral Synchronous. XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip-flops. XC3000 family: The XC5200 family does not provide an on-chip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 12 MHz are available.
VersaRing GRM VersaBlock Input/Output Blocks (IOBs)
VersaRing GRM VersaBlock GRM VersaBlock
Architectural Overview
Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks (Figure 2). General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM).
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
VersaRing
VersaRing
X4955
Figure 1: XC5200 Architectural Overview
VersaBlock: Abundant Local Routing Plus Versatile Logic
GRM
The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 3. Each LC contains a 4-input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for FPGAs. The storage device is configurable as either a D flip-flop or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions.
4
4
24 24
TS
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CLB
LC3
4 4 4
LC2 LC1 LC0
4 4
LIM
4 4
Direct Connects
X5707
Figure 2: VersaBlock
CO DO DI D F4 F3 F2 F1 X CI CE CK CLR
X4956
Q
FD F
Figure 3: XC5200 Logic Cell (Four LCs per CLB)
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The XC5200 CLB consists of four LCs, as shown in Figure 4. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement 5-input functions. The challenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect -- the Local Interconnect Matrix (LIM) and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 2. The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes. The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a "sea of logic cells." Each Versa-Block has four 3-state buffers that share a common enable line and directly drive horizontal and vertical Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. These resources also minimize local routing congestion and improve the efficiency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both fine-grain and coarse-grain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions.
LC3
DI
CO DO D Q
F4 F3 F2 F1
FD F
X
LC2
DO DI D F4 F3 F2 F1 X Q
VersaRing I/O Interface
The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-to-gate ratio and decreasing the cost per I/O. A "freeway" of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic. These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manufactured concurrent with the logic design.
FD F
LC1
DO DI D F4 F3 F2 F1 X Q
FD F
LC0
DO DI D F4 F3 F2 F1 X CI CE CK CLR
X4957
Q
FD F
General Routing Matrix
The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy -- a series of
Figure 4: Configurable Logic Block
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single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each Versa-Block. Throughout the XC5200 interconnect, an efficient multiplexing scheme, in combination with three layer metal (TLM), was used to improve the overall efficiency of silicon usage.
Detailed Functional Description
Configurable Logic Blocks (CLBs)
Figure 4 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a D-Type flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are: * An independent 5-input LUT by combining two 4-input LUTs. * High-speed carry propagate logic. * High-speed pattern decoding. * High-speed direct connection to flip-flop D-inputs. * Individual selection of either a transparent, level-sensitive latch or a D flip-flop. * Four 3-state buffers with a shared Output Enable.
Performance Overview
The XC5200 family has been benchmarked with many designs running synchronous clock rates beyond 66 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. A rough estimate of timing can be made by assuming 3-6 ns per logic level, which includes direct-connect routing delays, depending on speed grade. More accurate estimations can be made using the information in the Switching Characteristic Guideline section.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from LC0 and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be reconfigured dynamically to perform different functions at different times. Reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product time-to-market.
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CO DI D FD I1 I2 I3 I4 F4 F3 F2 F1 DO Q
F
X
LC1
F5_MUX DO I5 DI D FD F4 F3 F2 F1 Q out Qout
F CI CE CK CLR
X
LC0
X5710
5-Input Function
Figure 5: Two LUTs in Parallel Combined to Create a 5-input Function
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carry out A3 or B3
CO DI
DO D Q FD
carry3
DI
CO
DO
D
F4 F3 F2 F1
Q FD
A3 and B3 to any two
F4 F3 F2 F1
CY_MUX
XOR
XOR X sum3
X half sum3
LC3
A2 or B2
DI
LC3
DI DO
DO carry2 D Q FD
D
F4 F3 F2 F1
Q FD
A2 and B2 to any two
F4 F3 F2 F1
CY_MUX
XOR
X
half sum2
XOR X
sum2
LC2
A1 or B1
DI
LC2
DI DO
DO carry1 D Q FD
D
F4 F3 F2 F1
Q FD
A1 and B1 to any two
F4 F3 F2 F1
CY_MUX
XOR
X
half sum1
XOR X
sum1
LC1
A0 or B0 DI
LC1
carry0
DI DO
DO D Q FD
D
F4 F3 F2 F1
Q FD
A0 and B0 to any two
F4 F3 F2 F1
CY_MUX
XOR
X CI CE CK CLR
half sum0
XOR X CI CE CK CLR
sum0
LC0
LC0
0
carry in
CY_MUX F=0
Initialization of carry chain (One Logic Cell)
X5709
Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate
Carry Function
The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit high-speed carry propagate per logic cell (four bits per CLB). While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic function. Figure 6 represents an example of an adder function. The carry propagate is performed on the CLB shown,
which also generates the half-sum for the four-bit adder. An adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The carry chain can propagate vertically up a column of CLBs. The XC5200 library contains a set of Relationally-Placed Macros (RPMs) and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement cus-
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tomized RPMs, freeing the designer from the need to become an expert on architectures.
cascade out
results or other incoming data in flip-flops, and connect their outputs to the interconnect network as well. The CLB storage elements can also be configured as latches. Table 3: CLB Storage Element Functionality (active rising edge is shown)
CO DI DO out
D
A15 A14 A13 A12 F4 F3 F2 F1 AND CY_MUX
Q
FD
Mode Power-Up or GR Flip-Flop
CK X X __/ 0 1 0 X
CE X X 1* X 1* 1* 0
CLR X 1 0* 0* 0* 0* 0*
D X X D X X D X
Q 0 0 D Q Q D Q
X
LC3
DI D
CY_MUX A11 A10 A9 A8 DO
Q
FD
Latch Both
F4 F3 F2 F1
AND X
LC2
DI DO
Legend: X __/ 0* 1*
Don't care Rising edge Input is Low or unconnected (default value) Input is High or unconnected (default value)
D
A7 A6 A5 A4 F4 F3 F2 F1 AND CY_MUX
Q
FD
Data Inputs and Outputs
X
LC1
DI DO
D
A3 A2 A1 A0 F4 F3 F2 F1 CI cascade in CE CK CLR AND CY_MUX
Q
FD
The source of a storage element data input is programmable. It is driven by the function F, or by the Direct In (DI) block input. The flip-flops or latches drive the Q CLB outputs. Four fast feed-through paths from DI to DO are available, as shown in Figure 4. This bypass is sometimes used by the automated router to repower internal signals. In addition to the storage element (Q) and direct (DO) outputs, there is a combinatorial output (X) that is always sourced by the Lookup Table.
X5708
7
X
LC0
CY_MUX F=0 Initialization of carry chain (One Logic Cell)
Figure 7: XC5200 CY_MUX Used for Decoder Cascade Logic
The four edge-triggered D-type flip-flops or level-sensitive latches have common clock (CK) and clock enable (CE) inputs. Any of the clock inputs can also be permanently enabled. Storage element functionality is described in Table 3.
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 7 illustrates how the 4-input function generators can be configured to take advantage of these four cascaded CY_MUXes. Note that AND and OR cascading are specific cases of a general decode. In AND cascading all bits are decoded equal to logic one, while in OR cascading all bits are decoded equal to logic zero. The flexibility of the LUT achieves this result. The XC5200 library contains gate macros designed to take advantage of this function.
Clock Input
The flip-flops can be triggered on either the rising or falling clock edge. The clock pin is shared by all four storage elements with individual polarity control. Any inverter placed on the clock input is automatically absorbed into the CLB.
Clock Enable
The clock enable signal (CE) is active High. The CE pin is shared by the four storage elements. If left unconnected for any, the clock enable for that storage element defaults to the active state. CE is not invertible within the CLB.
CLB Flip-Flops and Latches
The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial
Clear
An asynchronous storage element input (CLR) can be used to reset all four flip-flops or latches in the CLB. This input
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can also be independently disabled for any flip-flop. CLR is active High. It is not invertible within the CLB.
STARTUP PAD IBUF GR GTS Q2 Q3 Q1Q4 CLK DONEIN
X9009
Three-State Buffers
The XC5200 family has four dedicated Three-State Buffers (TBUFs, or BUFTs in the schematic library) per CLB (see Figure 9). The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLB output enable (TS) control signal drives the enable to all four buffers. Each TBUF can drive up to two horizontal and/or two vertical Longlines. These 3-state buffers can be used to implement multiplexed or bidirectional buses on the horizontal or vertical longlines, saving logic resources. The 3-state buffer enable is an active-High 3-state (i.e. an active-Low enable), as shown in Table 4. Table 4: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN
Figure 8: Schematic Symbols for Global Reset
Global Reset
A separate Global Reset line clears each storage element during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GR) does not compete with other routing resources; it uses a dedicated distribution network. GR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GR pin of the STARTUP symbol. (See Figure 9.) A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Reset signal. Alternatively, GR can be driven from any internal node.
Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. The longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undefined floating levels. However, it is overridden by any driver. To ensure the longline goes high when no buffers are on, add an additional BUFT to drive the output High during all of the previously undefined states. Figure 10 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal.
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC5200 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline flip-flops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB flip-flop, place the appropriate library symbol. For example, FDCE is a D-type flip-flop with clock enable and asynchronous clear. The corresponding latch symbol is called LDCE. In XC5200-Series devices, the flip-flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices. The CLB setup time is specified between the function generator inputs and the clock input CK. Therefore, the specified CLB flip-flop setup time includes the delay through the function generator.
TS
CLB CLB LC3 LC2 LC1 LC0
Horizontal Longlines
X9030
Figure 9: XC5200 3-State Buffers
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~100 k
Z = DA * A + DB * B + DC * C + DN * N
DA BUFT A "Weak Keeper"
DB BUFT B
DC BUFT C
DN BUFT N
X6466
Figure 10: 3-State Buffers Implement a Multiplexer
Input/Output Blocks
User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals. The I/O block, shown in Figure 11, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. The input buffer has globally selected CMOS or TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set-up and hold times. Minimum ESD protection is 3 KV using the Human Body Model. Table 5: Supported Sources for XC5200-Series Device Inputs XC5200 Input Mode 5 V, 5 V, TTL CMOS Unreliable Data
Source Any device, Vcc = 3.3 V, CMOS outputs Any device, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, CMOS outputs
Optional Delay Guarantees Zero Hold Time
XC5200 devices do not have storage elements in the IOBs. However, XC5200 IOBs can be efficiently routed to CLB flip-flops or latches to store the I/O signals.
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Vcc
Input Buffer
Delay
Pullup
I
Output Buffer
PAD
Pulldown
O T
The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input flip-flop setup time is defined between the data measured at the device I/O pin and the clock input at the CLB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the CLB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the software default. The XC5200 IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC5200 global clock buffers. (See "Global Lines" on page 96 for a description of the global clock buffers in the XC5200.) For a shorter input register setup time, with
X9001
Slew Rate Control
Figure 11: XC5200 I/O Block
IOB Input Signals
The XC5200 inputs can be globally configured for either TTL (1.2V) or CMOS thresholds, using an option in the bitstream generation software. There is a slight hysteresis of about 300mV. The inputs of XC5200-Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC5200-Series device inputs are shown in Table 5.
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non-zero hold, attach a NODELAY attribute or property to the flip-flop or input buffer. For XC5200 devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For some XC5200 devices, additional internal Power/Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC5200 devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC5200 Series. XC5200-Series devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 11) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to Global Reset. See Figure 8 on page 90 for details. Alternatively, GTS can be driven from any internal node.
IOB Output Signals
Output signals can be optionally inverted within the IOB, and pass directly to the pad. As with the inputs, a CLB flip-flop or latch can be used to store the output signal. An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB. The XC5200 devices provide a guaranteed output sink current of 8 mA. Supported destinations for XC5200-Series device outputs are shown in Table 6.(For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.) An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 12.) Table 6: Supported Destinations for XC5200-Series Outputs XC5200 Output Mode 5 V, CMOS some1
Destination XC5200 device, VCC=3.3 V, CMOS-threshold inputs Any typical device, VCC = 3.3 V, CMOS-threshold inputs Any device, VCC = 5 V, TTL-threshold inputs Any device, VCC = 5 V, CMOS-threshold inputs
1. Only if destination device has 5-V tolerant inputs
OPAD OBUFT
X6702
Other IOB Options
There are a number of other programmable options in the XC5200-Series IOB. Pull-up and Pull-down Resistors
Figure 12: Open-Drain Output
Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.
Programmable IOB pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls
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to Vcc. The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is 20 k - 100 k. This high value makes them unsuitable as wired-AND pull-up resistors. The pull-up resistors for most user-programmable IOBs are active during the configuration process. See Table 13 on page 124 for a list of pins with pull-ups active before and during configuration. After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. JTAG Support Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, simplifying board-level testing. More information is provided in "Boundary Scan" on page 98.
OSCS OSC1 OSC2
CK_DIV
OSC1 OSC2
5200_14
Figure 13: XC5200 Oscillator Macros
VersaBlock Routing
The General Routing Matrix (GRM) connects to the Versa-Block via 24 bidirectional ports (M0-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these 24 ports. Four 3-statable unidirectional signals (TQ0-TQ3) drive out of the VersaBlock directly onto the horizontal and vertical Longlines. Two horizontal global nets and two vertical global nets connect directly to every CLB clock pin; they can connect to other CLB inputs via the GRM. Each CLB also has four unidirectional direct connects to each of its four neighboring CLBs. These direct connects can also feed directly back to the CLB (see Figure 14). In addition, each CLB has 16 direct inputs, four direct connections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM.
7
Oscillator
XC5200 devices include an internal oscillator. This oscillator is used to clock the power-on time-out, clear configuration memory, and source CCLK in Master configuration modes. The oscillator runs at a nominal 12 MHz frequency that varies with process, Vcc, and temperature. The output CCLK frequency is selectable as 1 MHz (default), 6 MHz, or 12 MHz. The XC5200 oscillator divides the internal 12-MHz clock or a user clock. The user then has the choice of dividing by 4, 16, 64, or 256 for the "OSC1" output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the "OSC2" output. The division is specified via a "DIVIDEn_BY=x" attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. These frequencies can vary by as much as -50% or + 50%. The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specified (see Figure 13).
Local Interconnect Matrix
The Local Interconnect Matrix (LIM) is built from input and output multiplexers. The 13 CLB outputs (12 LC outputs plus a Vcc/GND signal) connect to the eight VersaBlock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feedback path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight multiplexer outputs can connect to the GRM through the bidirectional M0-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB.
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To GRM M0-M23
24
8
Global Nets
4
TS COUT 4 4 To Longlines and GRM TQ0-TQ3
North South East West
4
CLB
4 5 4 4
LC3 LC2 LC1 LC0
3
Input Multiplexers
5
3 VCC /GND 3
Output Multiplexers
8 4
4
Direct to East
5
5 Direct North CLK 4 Feedback 4 CE CLR CIN
3
Direct West
4 4
Direct South
X5724
Figure 14: VersaBlock Details CLB inputs have several possible sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers, and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The flexibility of LUT input swapping and LUT mapping compensates for this limitation. For example, if a 2-input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT. The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce pin-to-pin set-up time, clock-to-out, and combinational propagation delay. Direct connects from the input buffers to the CLB DI pin (direct flip-flop input) are only available on the left and right edges of the device. CLB look-up table inputs and combinatorial/registered outputs have direct connects to input/output buffers on all four sides. The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths.
Direct Connects
The unidirectional direct-connect segments are connected to the logic input/output pins through the CLB input and output multiplexer arrays, and thus bypass the general routing matrix altogether. These lines increase the routing channel utilization, while simultaneously reducing the delay incurred in speed-critical connections.
General Routing Matrix
The General Routing Matrix, shown in Figure 15, provides flexible bidirectional connections to the Local Interconnect
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Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A pro-
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
GRM VersaBlock
1
2
GRM VersaBlock GRM VersaBlock GRM VersaBlock
3 4
7
Six Levels of Routing Hierarchy 1 2 3 4 5 6 LIM
Single-length Lines Double-length Lines
GRM
24 24
4
4
TS CLB
LC3
Direct Connects Longlines and Global Lines Local Interconnect Matrix Logic Cell Feedthrough Path (Contained within each Logic Cell)
4 4 4
LC2 LC1
4 4
6 LC0
LIM
4 4
5
Direct Connects
X4963
Figure 15: XC5200 Interconnect Structure grammable interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. A collection of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and associated routing segments combine to provide a powerful interconnect hierarchy: * Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions. Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (non-neighboring) CLBs in four directions. Eight horizontal and eight vertical bidirectional Longline
*
*
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segments span the width and height of the chip, respectively. Two low-skew horizontal and vertical unidirectional global-line segments span each row and column of the chip, respectively. carry/cascade logic described above, implementing a wide logic function in place of the wired function. In the case of 3-state bus applications, the user must insure that all states of the multiplexing function are defined. This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated.
Single- and Double-Length Lines
The single- and double-length bidirectional line segments make up the bulk of the routing channels. The double-length lines hop across every other CLB to reduce the propagation delays in speed-critical nets. Regenerating the signal strength is recommended after traversing three or four such segments. Xilinx place-and-route software automatically connects buffers in the path of the signal as necessary. Single- and double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto single- and double-length lines. As a general rule, Longline and global-line connections to the general routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix.
Global Lines
Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines, as shown in Figure 16. This network is intended for high-fanout clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads. The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the FPGA. The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals. Four clock input pads at the corners of the chip, as shown in Figure 16, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic. PIPs from several routing channels within the VersaRing can also be configured to drive the global-line buffers. Details of all the programmable interconnect for a CLB is shown in Figure 17.
Longlines
Longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half-lines. Longlines are driven by the 3-state buffers in each CLB, and are driven by similar buffers at the periphery of the array from the VersaRing I/O Interface. Bus-oriented designs are easily implemented by using Longlines in conjunction with the 3-state buffers in the CLB and in the VersaRing. Additionally, weak keeper cells at the periphery retain the last valid logic level on the Longlines when all buffers are in 3-state mode. Longlines connect to the single-length or double-length lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PIPs in the General Routing Matrix is not possible. Again, as a general rule, long- and global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix. The XC5200 family has no pull-ups on the ends of the Longlines sourced by TBUFs, unlike the XC4000 Series. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing functions requiring pull-ups for undefined states (i.e., bus applications) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the
GCK1
GCK4
GCK2
GCK3
X5704
Figure 16: Global Lines
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.
x9010
LONG CARRY DOUBLE SINGLE
CLB
7
DIRECT
GLOBAL
DIRECT
DIRECT
GLOBAL
Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB
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DOUBLE
SINGLE
LONG
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The VersaRing, shown in Figure 18, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The VersaRing decouples the core logic from the I/O pads. Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on the other side. XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. When the boundary scan configuration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. Boundary-scan operation is independent of individual IOB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after configuration provides flexibility for interconnect testing.
Pad 10 Pad
VersaRing
8 8 2 2 GRM 2 2 8
Interconnect
4 4 Pad Pad
Also, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This technique partially compensates for the lack of INTEST support. The user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note XAPP 017: "Boundary Scan in XC4000 and XC5200 Series devices" Figure 19 on page 99 is a diagram of the XC5200-Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. The public boundary-scan instructions are always available prior to configuration. After configuration, the public instructions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA device, and to read back the configuration data. All of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the UserRegister are provided (Reset, Update, and Shift), repre-
VersaBlock
8 2 2 GRM 10
8
Pad Pad
Interconnect
Pad 4 VersaBlock 4 2 8 2 8
X5705
Pad
Figure 18: VersaRing I/O Interface
Boundary Scan
The "bed of nails" has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE boundary scan standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.
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senting the decoding of the corresponding state of the boundary-scan internal state machine.
DATA IN
1 0 D Q D
sd Q
LE 1 IOB.O IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0
0 1
LE
IOB
IOB
1 0
sd D Q D Q
IOB
IOB LE
IOB
IOB IOB.I 1 0 1 sd D Q D Q
IOB
IOB
IOB
IOB
0
IOB
IOB
LE 1 IOB.O IOB.T 0
IOB
BYPASS REGISTER INSTRUCTION REGISTER
IOB
TDI
M TDO U X
0 1 0 D Q D sd Q 1
7
LE M U TDO X INSTRUCTION REGISTER BYPASS REGISTER TDI
1 IOB 0 D Q D
sd Q
IOB
IOB
IOB
LE
IOB
IOB
1 IOB.I 0
IOB
IOB
1 0 D Q D
sd Q
IOB
IOB LE
IOB
IOB IOB.O DATAOUT IOB IOB IOB IOB IOB SHIFT/ CAPTURE CLOCK DATA REGISTER UPDATE
0 1
IOB
IOB
EXTEST
X1523_01
Figure 19: XC5200-Series Boundary Scan Logic
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XC5200-Series devices can also be configured through the boundary scan logic. See XAPP 017 for more information.
Bit Sequence
The bit sequence within each IOB is: 3-State, Out, In. The data-register cells for the TAP pins TMS, TCK, and TDI have an OR-gate that permanently disables the output buffer if boundary-scan operation is selected. Consequently, it is impossible for the outputs in IOBs used by TAP inputs to conflict with TAP operation. TAP data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data. The primary global clock inputs (PGCK1-PGCK4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if necessary, it is possible to drive the clock input from boundary scan. The external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clock-pad IOB. If the clock-pad IOBs are used for non-clock signals, the data may be overwritten normally. Pull-up and pull-down resistors remain active during boundary scan. Before and during configuration, all pins are pulled up. After configuration, the choice of internal pull-up or pull-down resistor must be taken into account when designing test vectors to detect open-circuit PC traces. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Table 8. The device-specific pinout tables for the XC5200 Series include the boundary scan locations for each IOB pin. Table 8: Boundary Scan Bit Sequence Bit Position Bit 0 (TDO) Bit 1 ... ... ... Bit N (TDI) I/O Pad Location Top-edge I/O pads (right to left) ... Left-edge I/O pads (top to bottom) Bottom-edge I/O pads (left to right) Right-edge I/O pads (bottom to top) BSCANT.UPD
Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-State pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions, USER1 and USER2. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).
Instruction Set
The XC5200-Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 7. Table 7: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Test TDO Source Selected EXTEST DR SAMPLE/PR DR ELOAD USER 1 BSCAN. TDO1 USER 2 BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved -- BYPASS Bypass Register I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled -- --
BSDL (Boundary Scan Description Language) files for XC5200-Series devices are available on the Xilinx web site in the File Download area.
Including Boundary Scan
If boundary scan is only to be used during configuration, no special elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after configuration. To indicate that boundary scan remain enabled after configuration, include the BSCAN library symbol and connect pad symbols to the TDI, TMS, TCK and TDO pins, as shown in Figure 20.
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Typically, a 0.1 F capacitor connected near the Vcc and Ground pins of the package will provide adequate decoupling. Output buffers capable of driving/sinking the specified 8 mA loads under specified worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical.
Optional IBUF BSCAN
RESET UPDATE SHIFT TDI TMS TCK TDO DRCK IDLE SEL1 SEL2
To User Logic
From User Logic
TDO1 TDO2
To User Logic
X9000
Figure 20: Boundary Scan Schematic Example Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK.
GND Ground and Vcc Ring for I/O Drivers
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process.
Vcc
Vcc
Logic Power Grid
7
GND
To prevent activation of boundary scan during configuration, do either of the following: * * TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Low--do not toggle this clock input.
X5422
Figure 21: XC5200-Series Power Distribution
Pin Descriptions
There are three types of pins in the XC5200-Series devices: * * * Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins.
For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017, "Boundary Scan in XC4000 and XC5200 Devices."
Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 21. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled.
Before and during configuration, all outputs not used for the configuration process are 3-stated and pulled high with a 20 k - 100 k pull-up resistor. After configuration, if an IOB is unused it is configured as an input with a 20 k - 100 k pull-up resistor. Device pins for XC5200-Series devices are described in Table 9. Pin functions during configuration for each of the seven configuration modes are summarized in "Pin Func-
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tions During Configuration" on page 124, in the "Configuration Timing" section. Table 9: Pin Descriptions I/O I/O After During Config. Config. Pin Name Permanently Dedicated Pins VCC I I
Pin Description
Five or more (depending on package) connections to the nominal +5 V supply voltage. All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Four or more (depending on package type) connections to Ground. All must be conGND I I nected. During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and CCLK I or O I can be selected as the Readback Clock. There is no CCLK High time restriction on XC5200-Series devices, except during Readback. See "Violating the Maximum High and Low Time Specification for the Readback Clock" on page 113 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE can be configured to delay the global logic initialization and the enabling of outputs. DONE I/O O The exact timing, the clock source for the Low-to-High transition, and the optional pull-up resistor are selected as options in the program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA PROGRAM I I executes a complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAM pin has an optional weak pull-up after configuration. User I/O Pins That Can Have Special Functions During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in Asynchronous Peripheral mode, if a read operation is performed when the device is selected. O I/O RDY/BUSY After configuration, RDY/BUSY is a user-programmable I/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the A0-A17 outputs is preceded by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked O I/O RCLK PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. As Mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. After configuration, M0, M1, and M2 become user-programmable I/O. M0, M1, M2 I I/O During configuration, these pins have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down resistor value of 3.3 k is recommended for other modes. If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output, after configuration is completed. TDO O O This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.
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Table 9: Pin Descriptions (Continued) I/O I/O After During Config. Config.
Pin Name
TDI, TCK, TMS
I
HDC
O
LDC
O
INIT
I/O
GCK1 GCK4
Weak Pull-up
CS0, CS1, WS, RS
I
A0 - A17 D0 - D7 DIN
O I I
DOUT
O
Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. I/O If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibor I ited once configuration is completed, and these pins become user-programmable I/O. (JTAG) In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as I/O a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a I/O control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used I/O to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 50 to 250 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. I or I/O The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input pad symbol connected directly to the input of a BUFG symbol is automatically placed on one of these pins. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output -- High if Ready, Low if Busy -- I/O and drives D0 - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. During Master Parallel configuration, these 18 output pins address the configuration I/O EPROM. After configuration, they are user-programmable I/O pins. During Master Parallel, Peripheral, and Express configuration, these eight input pins reI/O ceive configuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained I/O FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin.
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Table 9: Pin Descriptions (Continued) I/O I/O After During Pin Description Config. Config. Pin Name Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor (20 k - 100 k) that defines the logic level as High.
Configuration
Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC5200-Series devices use several hundred bits of configuration data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The development system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format.
M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, Table 10: Configuration Modes Mode Master Serial Slave Serial Master Parallel Up Master Parallel Down Peripheral Synchronous* Peripheral Asynchronous Express Reserved M2 0 1 1 M1 0 1 0 M0 0 1 0 CCLK output input output Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide Byte-Wide Byte-Wide --
1
1
0
output
0 1 0 0
1 0 1 0
1 1 0 1
input output input --
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled prior to configuration to determine the configuration mode. After configuration, these pins can be used as auxiliary I/O connections. The development system does not use these resources unless they are explicitly specified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol. In XC5200-Series devices, the mode pins have weak pull-up resistors during configuration. With all three mode pins High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) After configuration, these pins can individually have weak pull-up or pull-down resistors, as specified in the design. A pull-down resistor value of 3.3k is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired.
Note :*Peripheral Synchronous can be considered byte-wide Slave Parallel
which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel configuration. The coding for mode selection is shown in Table 10. Note that the smallest package, VQ64, only supports the Master Serial, Slave Serial, and Express modes.A detailed description of each configuration mode, with timing information, is included later in this data sheet. During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during configuration are shown in Table 13 on page 124.
Master Modes
The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the configuration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, for compatibility with different microprocessor addressing conventions. The
Configuration Modes
XC5200 devices have seven configuration modes. These modes are selected by a 3-bit input code applied to the M2,
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Master Serial mode generates CCLK and receives the configuration data in serial form from a Xilinx serial-configuration PROM. CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12 MHz. Configuration always starts at the default slow frequency, then can switch to the higher frequency during the first frame. Frequency tolerance is -50% to +50%. Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, XC4000, and XC5200 Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. If the chain contains XC5200-Series devices, the master normally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 25 on page 109. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 25. The master device then generates additional CCLK pulses until it reaches its finish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really finish its configuration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC5200-Series device, not reaching F means that readback cannot be initiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the finish point F is reached. Timing is controlled using options in the bitstream generation software. XC5200 devices always have the same number of CCLKs in the power up delay, independent of the configuration mode, unlike the XC3000/XC4000 Series devices. To guarantee all devices in a daisy chain have finished the power-up delay, tie the INIT pins together, as shown in Figure 27. XC3000 Master with an XC5200-Series Slave Some designers want to use an XC3000 lead device in peripheral mode and have the I/O pins of the XC5200-Series devices all available for user I/O. Figure 22 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be configured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC5200-Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the byte-wide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously. Serial Daisy Chain Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 28 on page 114. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the length count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last configuration bit is received. Figure 25 on page 109 shows the start-up timing for an XC5200-Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM file formatter must be used to combine the bitstreams for a daisy-chained configuration.
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Pseudo Daisy Chain Multiple devices with different configurations can be connected together in a pseudo daisy chain, provided that all of the devices are in Express mode. A single combined bitstream is used to configure the chain of Express mode devices, but the input data bus must drive D0-D7 of each device. Tie High the CS1 pin of the first device to be configured, or leave it floating in the XC5200 since it has an internal pull-up. Connect the DOUT pin of each FPGA to the CS1 pin of the next device in the chain. The D0-D7 inputs are wired to each device in parallel. The DONE pins are wired together, with one or more internal DONE pull-ups activated. Alternatively, a 4.7 k external resistor can be used, if desired. (See Figure 37 on page 122.) CCLK pins are tied together. The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All devices in Express mode are synchronized to the DONE pin. User I/O for each device become active after the DONE pin for that device goes High. (The exact timing is determined by options to the bitstream generation software.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device in the chain has completed its configuration cycle. The status pin DOUT is pulled LOW two internal-oscillator cycles (nominally 1 MHz) after INIT is recognized as High, and remains Low until the device's configuration memory is full. Then DOUT is pulled High to signal the next device in the chain to accept the configuration data on the D7-D0 bus. All devices receive and recognize the six bytes of preamble and length count, irrespective of the level on CS1; but subsequent frame data is accepted only when CS1 is High and the device's configuration memory is not already full.
OE/T Reset 0 0 1 0 1 1 0 1 0 1 . etc .
Output Connected to CCLK
Active Low Output Active High Output
.
.
X5223
Figure 22: CCLK Generation for XC3000 Master Driving an XC5200-Series Slave
Express Mode
Express mode is similar to Slave Serial mode, except the data is presented in parallel format, and is clocked into the target device a byte at a time rather than a bit at a time. The data is loaded in parallel into eight different columns: it is not internally serialized. Eight bits of configuration data are loaded with every CCLK cycle, therefore this configuration mode runs at eight times the data rate of the other six modes. In this mode the XC5200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to an 80 MHz serial rate, because eight bits of configuration data are being loaded per CCLK cycle. An XC5210 in the Express mode, for instance, can be configured in about 2 ms. The Express mode does not support CRC error checking, but does support constant-field error checking. A length count is not used in Express mode. In the Express configuration mode, an external signal drives the CCLK input(s). The first byte of parallel configuration data must be available at the D inputs of the FPGA devices a short set-up time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 38 on page 123. Bitstream generation currently generates a bitstream sufficient to program in all configuration modes except Express. Extra CCLK cycles are necessary to complete the configuration, since in this mode data is read at a rate of eight bits per CCLK cycle instead of one bit per cycle. Normally the entire start-up sequence requires a number of bits that is equal to the number of CCLK cycles needed. An additional five CCLKs (equivalent to 40 extra bits) will guarantee completion of configuration, regardless of the start-up options chosen. Multiple slave devices with identical configurations can be wired with parallel D0-D7 inputs. In this way, multiple devices can be configured simultaneously.
Setting CCLK Frequency
For Master modes, CCLK can be generated in one of three frequencies. In the default slow mode, the frequency is nominally 1 MHz. In fast CCLK mode, the frequency is nominally 12 MHz. In medium CCLK mode, the frequency is nominally 6 MHz. The frequency range is -50% to +50%. The frequency is selected by an option when running the bitstream generation software. If an XC5200-Series Master is driving an XC3000- or XC2000-family slave, slow CCLK mode must be used. Slow mode is the default. Table 11: XC5200 Bitstream Format
Data Type Fill Byte Preamble Length Counter Fill Byte Value 11111111 11110010 COUNT(23:0) 11111111 Occurrences Once per bitstream
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Table 11: XC5200 Bitstream Format
Data Type Start Byte Data Frame * Cyclic Redundancy Check or Constant Field Check Fill Nibble Extend Write Cycle Postamble Fill Bytes (30) Start-Up Byte Value 11111110 DATA(N-1:0) CRC(3:0) or 0110 1111 FFFFFF 11111110 FFFF...FF FF Occurrences Once per data frame
CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vcc.
Table 12: Internal Configuration Data Structure VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22 PROM Size (bits) 42,416 70,704 106,288 165,488 237,744 Xilinx Serial PROM Needed XC1765D XC17128D XC17128D XC17256D XC17256D
Device
Once per device
Once per bitstream *Bits per Frame (N) depends on device size, as described for table 11.
Data Stream Format
The data stream ("bitstream") format is identical for all configuration modes, with the exception of Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream formats are shown in Table 11. Express mode data is shown with D0 at the left and D7 at the right. For all other modes, bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bit in each byte assigned to D0. The configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones (or 24 fill bits, in Express mode). This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 12). Each frame begins with a start field and ends with an error check. In all modes except Express mode, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are don't-cares; these bytes are not included in bitstreams created by the Xilinx software. In Express mode, only non-CRC error checking is supported. In all other modes, a selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes,
XC5202 XC5204 XC5206 XC5210 XC5215
Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill bits * + 24 extended write bits = (34 x number of Rows) + 100 * In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4 Number of Frames = (12 x number of Columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit = (12 x number of Columns) + 16 Program Data = (Bits per Frame x Number of Frames) + 48 header bits + 8 postamble bits + 240 fill bits + 8 start-up bits = (Bits per Frame x Number of Frames) + 304 PROM Size = Program Data
Cyclic Redundancy Check (CRC) for Configuration and Readback
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the configuration bitstream has four error bits at the end, as shown in Table 11. If a frame data error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 23. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Read Capture option not used). Statistically, one error out of 2048 might go undetected.
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Initialization
X2 01 2 3 4 5 6 7 8 9 10 11 12 13 14 X15 X16 15
This phase clears the configuration memory and establishes the configuration mode. The configuration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 MHz). An open-drain bidirectional signal, INIT, is released when the configuration memory is completely cleared. The device then tests for the absence of an external active-low level on INIT. The mode lines are sampled two internal clock cycles later (nominally 2 s). The master device waits an additional 32 s to 256 s (nominally 64-128 s) to provide adequate time for all of the slave devices to recognize the release of INIT as well. Then the master device enters the Configuration phase.
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
1
1
1
1
1 0 15 14 13 12 11 10 9
START BIT
8765
LAST DATA FRAME
CRC - CHECKSUM
Readback Data Stream
X1789
Figure 23: Circuit for Generating CRC-16
Configuration Sequence
There are four major steps in the XC5200-Series power-up configuration sequence. * * * * Power-On Time-Out Initialization Configuration Start-Up
Boundary Scan Instructions Available:
VCC 3V Yes
No
Generate One Time-Out Pulse of 4 ms
PROGRAM = Low Yes
The full process is illustrated in Figure 24.
Power-On Time-Out
An internal power-on reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA begin to operate (i.e., performs a write-and-read test of a sample pair of configuration memory bits), the programmable I/O buffers are 3-stated with active high-impedance pull-up resistors. A time-out delay -- nominally 4 ms -- is initiated to allow the power-supply voltage to stabilize. For correct operation the power supply must reach VCC(min) by the end of the time-out, and must not dip below it thereafter. There is no distinction between master and slave modes with regard to the time-out delay. Instead, the INIT line is used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For proper operation with XC3000 devices, the RESET signal, which is used in XC3000 to delay configuration, should be connected to INIT. If the time-out delay is insufficient, configuration should be delayed by holding the INIT pin Low until the power supply has reached operating levels. This delay is applied only on power-up. It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin Low. During all three phases -- Power-on, Initialization, and Configuration -- DONE is held Low; HDC, LDC, and INIT are active; DOUT is driven; and all I/O buffers are disabled.
EXTEST* SAMPLE/PRELOAD* BYPASS CONFIGURE*
(*only when PROGRAM = High)
Completely Clear Configuration Memory
~1.3 s per Frame
INIT High? if Master Yes Sample Mode Lines Master CCLK Goes Active after 50 to 250 s
No
Load One Configuration Data Frame
Frame Error No
Yes
Pull INIT Low and Stop
SAMPLE/PRELOAD BYPASS
Configuration memory Full Yes Pass Configuration Data to DOUT
No
CCLK Count Equals Length Count Yes Start-Up Sequence
No
F
EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK Operational
I/O Active
X9017
If Boundary Scan is Selected
Figure 24: Configuration Sequence
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Length Count Match
CCLK Period
CCLK
F DONE
XC2000
I/O
Global Reset F F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing Global Reset F DONE C1 C2 C3 C4 I/O C2 GSR Active C2 DONE IN F DONE C1, C2 or C3 I/O C3 C4 C3 C4
XC3000
DONE I/O
XC4000E/EX XC5200/
CCLK_NOSYNC
7
XC4000E/EX XC5200/
CCLK_SYNC
Di
GSR Active
Di+1
Di
Di+1
F
DONE C1 U2 U3 U4 I/O U2 GSR Active U2 DONE IN F DONE C1 U2 I/O U3 U4 U3 U4
XC4000E/EX XC5200/
UCLK_NOSYNC
XC4000E/EX XC5200/
UCLK_SYNC
Di
GSR Active
Di+1
Di+2
Synchronization Uncertainty
Di
Di+1
Di+2
UCLK Period
X6700
Figure 25: Start-up Timing
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The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream. Configuration will not begin until the internal configuration logic reset is released, which happens two cycles after INIT goes High. A master device's configuration is delayed from 32 to 256 s to ensure proper operation with any slave devices driven by the master device. The 0010 preamble code, included for all modes except Express mode, indicates that the following 24 bits represent the length count. The length count is the total number of configuration clocks needed to load the complete configuration data. (Four additional configuration clocks are required to complete the configuration process, as discussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. In Express mode, the length count bits are ignored, and DOUT is held Low, to disable the next device in the pseudo daisy chain. A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. In Express mode, when the first device is fully programmed, DOUT goes High to enable the next device in the chain.
Start-Up
Start-up is the transition from the configuration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic `wakes up' gracefully, that the outputs become active without causing contention with the configuration signals, and that the internal flip-flops are released from the global Reset at the right time. Figure 25 describes start-up timing for the three Xilinx families in detail. Express mode configuration always uses either CCLK_SYNC or UCLK_SYNC timing, the other configuration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a fixed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some flexibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000/XC5200 Series offers additional flexibility. The three events -- DONE going High, the internal Reset being de-activated, and the user I/O going active -- can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of software options in the bitstream generation software. The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os become active one clock later. Reset is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 25, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. XC4000/XC5200 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a configuration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system.
Delaying Configuration After Power-Up
To delay master mode configuration after power-up, pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 12.) Using an open-collector or open-drain driver to hold INIT Low before the beginning of master mode configuration causes the FPGA to wait after completing the configuration memory clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configuration process. A master device waits up to an additional 250 s to make sure that any slaves in the optional daisy chain have seen that INIT is High.
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When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active. If either of these two options is selected, and no user clock is specified in the design or attached to the device, the chip could reach a point where the configuration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the configuration memory is full, and the total number of configuration clocks received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a flip-flop Q0, shown in Figure 26. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. * * * The release of the open-drain DONE output The change of configuration-related pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. ship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence.
DONE Goes High to Signal End of Configuration
In all configuration modes except Express mode, XC5200-Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration. Two conditions have to be met in order for the DONE pin to go high: * * the chip's internal memory must be full, and the configuration length count must be met, exactly.
This is important because the counter that determines when the length count is met begins with the very first CCLK, not the first one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the first CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of configuration, the configuration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] -- which is sometimes interpreted as the device not configuring at all. If it is not possible to have the data ready at the time of the first CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. In Express mode, there is no length count. The DONE pin for each device goes High when the device has received its quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all are fully configured. Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software.
7
The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called "Start-up Timing Synchronous to Done In" and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called "Start-up Timing Not Synchronous to DONE In," and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. As a configuration option, the start-up control register beyond Q0 can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK If CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 25 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options. Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relation-
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after the DONE pin goes High. If CCLK is not clocked after DONE goes High, the outputs remain in their initial state -- 3-stated, with a 20 k - 100 k pull-up. The delay from
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XC5200 Series Field Programmable Gate Arrays
DONE High to active user I/O is controlled by an option to the bitstream generation software.
Q3 STARTUP Q2 Q1/Q4 DONE IN
* *
1 0 GR ENABLE GR INVERT STARTUP.GR STARTUP.GTS GTS INVERT GTS ENABLE 0
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL RESET OF ALL CLB FLIP-FLOPS/LATCHES
CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE)
GLOBAL 3-STATE OF ALL IOBs 1
Q
S
R
*
1 0 1 0
DONE " FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR
Q0
Q1
Q2
Q3
Q4
FULL LENGTH COUNT
1 S Q D Q D Q 0 M K K K D Q D Q
*
K
K
CLEAR MEMORY CCLK STARTUP.CLK USER NET 0 1
M
*
Figure 26: Start-up Logic
*
CONFIGURATION BIT OPTIONS SELECTED BY USER
X9002
Release of Global Reset After DONE Goes High
By default, Global Reset (GR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all flip-flops are held in their initial reset state. The delay from DONE High to GR inactive is controlled by an option to the bitstream generation software.
Configuration Through the Boundary Scan Pins
XC5200-Series devices can be configured through the boundary scan pins. For detailed information, refer to the Xilinx application note XAPP017, "Boundary Scan in XC4000 and XC5200 Devices."
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 25 on page 109. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used.
Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs.
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Note that in XC5200-Series devices, configuration data is not inverted with respect to configuration as it is in XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble the original bitstream, because the bitstream format differs from other modes. XC5200-Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 27. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with five dummy bits (all High) followed by the Start bit (Low) of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low.
IF UNCONNECTED, DEFAULT IS CCLK
The readback signals are located in the lower-left corner of the device.
Read Abort
When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected.
Violating the Maximum High and Low Time Specification for the Readback Clock
The readback clock has a maximum High and Low time specification. In some cases, this specification cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 11 and Table 12.
7
CLK MD0 READ_TRIGGER IBUF TRIG READBACK
DATA RIP OBUF
READ_DATA
MD1
X1786
Figure 27: Readback Schematic Example
Readback Options
Readback options are: Read Capture, Read Abort, and Clock Select. They are set with the bitstream generation software.
Read Capture
When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the CLB outputs and the IOB output and input signals. Note that while the bits describing configuration (interconnect and function generators) are not inverted, the CLB and IOB output signals are inverted. When the Read Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verification. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator.
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XC5200 Series Field Programmable Gate Arrays
Configuration Timing
The seven configuration modes are discussed in detail in this section. Timing specifications are included.
There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 28 shows a full master/slave system. An XC5200-Series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resistors during configuration.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble data--and all data that overflows the lead device--on its DOUT pin.
NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O
NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O VCC N/C
3.3 K
3.3 K
3.3 K
3.3 K N/C DOUT XC5200 MASTER SERIAL CCLK DIN VCC XC1700E 4.7 K CLK DATA VPP +5 V M0 M1 M2 DIN CCLK Spartan, XC4000E/EX, XC5200 SLAVE PROGRAM DONE DOUT
3.3 K
3.3 K
M0 M1 M2
M0 M1 PWRDN M2 DIN CCLK XC3100A SLAVE DOUT
PROGRAM DONE
LDC INIT
CEO CE RESET/OE (Low Reset Option Used)
INIT
RESET D/P
INIT
PROGRAM
X9003_01
Figure 28: Master/Slave Serial Mode Circuit Diagram
DIN 1 TDCC CCLK
Bit n 2 TCCD
Bit n + 1 5 TCCL
4 TCCH DOUT (Output) Bit n - 1
3 TCCO Bit n
X5379
CCLK
Description DIN setup DIN hold DIN to DOUT High time Low time Frequency
1 2 3 4 5
Symbol TDCC TCCD TCCO TCCH TCCL FCC
Min 20 0 45 45
Max
30
10
Units ns ns ns ns ns MHz
Note:
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 29: Slave Serial Mode Programming Switching Characteristics
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XC5200 Series Field Programmable Gate Arrays Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble data--and all data that overflows the lead device--on its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In the bitstream generation software, the user can specify Fast ConfigRate, which, starting several bits into the first frame, increases the CCLK frequency by a factor of twelve. The value increases from a nominal 1 MHz, to a nominal 12 MHz. Be sure that the serial PROM and slaves are fast enough to support this data rate. The Medium ConfigRate option changes the frequency to a nominal 6 MHz. XC2000, XC3000/A, and XC3100A devices do not support the Fast or Medium ConfigRate options. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but LDC is then restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN, provided the DONE before I/O enable option is invoked. Figure 28 on page 114 shows a full master/slave system. The leftmost device is in Master Serial mode. Master Serial mode is selected by a <000> on the mode pins (M2, M1, M0).
CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2
7
n
X3223
Serial DOUT (Output)
n-3
n-2
n-1
CCLK
Description DIN setup DIN hold
Symbol 1 TDSCK 2 TCKDS
Min 20 0
Max
Units ns ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode.
Figure 30: Master Serial Mode Programming Switching Characteristics In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decrementing the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble data--and all data that overflows the lead device--on its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and can load its configuration bitstream from either end of the memory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, M0). The EPROM addresses start at 00000 and increment. Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement.
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XC5200 Series Field Programmable Gate Arrays
3.3 K
HIGH or LOW
TO DIN OF OPTIONAL DAISY-CHAINED FPGAS N/C N/C TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS
M0
M1
M2 CCLK
NOTE:M0 can be shorted to Ground if not used as I/O. VCC
DOUT A17 XC5200 Master Parallel A16 A15 A14 INIT A13 A12 A11 A10 PROGRAM D7 D6 D5 D4 D3 D2 D1 D0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DONE ... ... ... ... ... A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE CE D7 D6 D5 D4 D3 D2 D1 D0 DONE INIT EPROM (8K x 8) (OR LARGER) USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS M0 DIN M1 M2 DOUT
4.7K
CCLK XC5200/ XC4000E/EX/ Spartan SLAVE PROGRAM
DATA BUS PROGRAM
8
X9004_01
Figure 31: Master Parallel Mode Circuit Diagram
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XC5200 Series Field Programmable Gate Arrays
.
A0-A17 (output) Address for Byte n Address for Byte n + 1 1 TRAC D0-D7 Byte 2 TDRC RCLK (output) 7 CCLKs CCLK 3 TRCD
CCLK (output)
DOUT (output)
D6 Byte n - 1
D7
X6078
CCLK
Note:
Description Delay to Address valid Data setup time Data hold time
1 2 3
Symbol TRAC TDRC TRCD
Min 0 60 0
Max 200
Units ns ns ns
7
1. At power-up, VCC must rise from 2.0 V to VCC min in less then 25 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is Valid. 2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 32: Master Parallel Mode Programming Switching Characteristics
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XC5200 Series Field Programmable Gate Arrays Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisy-chained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, M0).
NOTE: M2 can be shorted to Ground if not used as I/O
N/C 3.3 k N/C
M0 M1
CLOCK CCLK
M2 OPTIONAL DAISY-CHAINED FPGAs DOUT
M0 M1 CCLK
M2
DATA BUS
8 D0-7
DIN
DOUT
VCC
4.7 k
XC5200 SYNCHRONOUS PERIPHERAL
XC5200E/EX SLAVE
CONTROL SIGNALS 3.3 k PROGRAM
RDY/BUSY INIT DONE INIT DONE
PROGRAM
PROGRAM
X9005
Figure 33: Synchronous Peripheral Mode Circuit Diagram
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XC5200 Series Field Programmable Gate Arrays
TCCL
CCLK
1
TIC
2 D0 - D7
BYTE 0
3
TCD
INIT
TDC
BYTE 1
BYTE 0 OUT DOUT 0 1 2 3 4 5 6 7
BYTE 1 OUT 0 1
RDY/BUSY
X6096
CCLK
Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency
Symbol 1 TIC 2 TDC 3 TCD TCCH TCCL FCC
Min 5 60 0 50 60
Max
8
Units s ns ns ns ns MHz
7
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal. 4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics
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XC5200 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overflows the lead device) on its DOUT pin. The RDY/BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
3.3 k
The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.
Status Read
The logic AND condition of the CS0, CS1 and RS inputs puts the device status on the Data bus. * * * D7 High indicates Ready D7 Low indicates Busy D0 through D6 go unconditionally High
It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the final byte transfer. If this transfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 25 on page 109). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by the software, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, M0).
N/C N/C
M0
M1
M2
M0
M1
M2
DATA BUS
8
D0-7
CCLK OPTIONAL DAISY-CHAINED FPGAs DOUT
CCLK
DIN
DOUT
VCC
ADDRESS BUS
ADDRESS DECODE LOGIC
CS0
4.7 k
4.7 k
XC5200 ASYNCHRONOUS PERIPHERAL
...
CS1 RS WS
XC5200/ XC4000E/EX SLAVE
CONTROL SIGNALS
RDY/BUSY INIT DONE REPROGRAM
3.3 k
INIT DONE PROGRAM
PROGRAM
X9006
Figure 35:
Asynchronous Peripheral Mode Circuit Diagram
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XC5200 Series Field Programmable Gate Arrays
Write to LCA WS/CS0 Read Status RS, CS0
RS, CS1
WS, CS1
1
TCA 2 3 TDC TCD 7
READY BUSY
4
D7
D0-D7
CCLK
TWTRB 4
RDY/BUSY
6
TBUSY
DOUT
Previous Byte D6
D7
D0
D1
D2
X6097
Write
RDY
Description Effective Write time (CSO, WS=Low; RS, CS1=High DIN setup time DIN hold time RDY/BUSY delay after end of Write or Read RDY/BUSY active after beginning of Read RDY/BUSY Low output (Note 4)
Symbol 1 TCA 2 3 4 7 6 TBUSY TDC TCD TWTRB
Min 100 60 0
Max
Units ns ns ns ns ns CCLK periods
7
60 60 2 9
Notes: 1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics
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XC5200 Series Field Programmable Gate Arrays Express Mode
Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the configuration data shift registers. A CCLK frequency of 10 MHz is equivalent to an 80 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not support CRC error checking, but does support constant-field error checking. In Express mode, an external signal drives the CCLK input of the FPGA device. The first byte of parallel configuration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. If the first device is configured in Express mode, additional devices may be daisy-chained only if every device in the chain is also configured in Express mode. CCLK pins are tied together and D0-D7 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). Frame data is accepted only when CS1 is High and the device's configuration memory is not already full. The status pin DOUT is pulled Low two internal-oscillator cycles after INIT is recognized as High, and remains Low until the device's configuration memory is full. DOUT is then pulled High to signal the next device in the chain to accept the configuration data on the D0-D7 bus. The DONE pins of all devices in the chain should be tied together, with one or more active internal pull-ups. If a large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is activated by default. It can be deactivated using an option in the bitstream generation software. XC5200 devices in Express mode are always synchronized to DONE. The device becomes active after DONE goes High. DONE is an open-drain output. With the DONE pins tied together, therefore, the external DONE signal stays low until all devices are configured, then all devices in the daisy chain become active simultaneously. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been configured. Express mode is selected by a <010> on the mode pins (M2, M1, M0).
VCC NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O 3.3 k 8 To Additional Optional Daisy-Chained Devices
M0
M1
M2
M0
M1
M2
CS1 DATA BUS 8 VCC D0-D7 XC5200
DOUT 8
CS1 D0-D7
DOUT
Optional Daisy-Chained XC5200
4.7K PROGRAM INIT PROGRAM INIT CCLK DONE PROGRAM INIT CCLK DONE
CCLK
To Additional Optional Daisy-Chained Devices
X6611_01
Figure 37: Express Mode Circuit Diagram
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XC5200 Series Field Programmable Gate Arrays
CCLK 1 TIC
INIT TCD 3 2T DC D0-D7
BYTE 0 BYTE 1 BYTE 2 BYTE 3
Serial Data Out (DOUT) FPGA Filled Internal INIT
RDY/BUSY
CS1
X5087
CCLK
Description INIT (High) Setup time required DIN Setup time required DIN hold time required CCLK High time CCLK Low time CCLK frequency
1 2 3
Symbol TIC TDC TCD TCCH TCCL FCC
Min 5 30 0 30 30
Max
10
Units s ns ns ns ns MHz
7
Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully configured.
Figure 38: Express Mode Programming Switching Characteristics
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XC5200 Series Field Programmable Gate Arrays Table 13.
SLAVE <1:1:1>
Pin Functions During Configuration
CONFIGURATION MODE: MASTER-SER <0:0:0> SYN.PERIPH <0:1:1> ASYN.PERIPH MASTER-HIGH MASTER-LOW <1:0:1> <1:1:0> <1:0:0> A16 A17 TDI TCK TMS M1 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK (O) TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 EXPRESS <0:1:0> USER OPERATION GCK1-I/O I/O TDI-I/O TCK-I/O TMS-I/O I/O I/O I/O I/O GCK2-I/O I/O I/O I/O I/O DONE PROGRAM I/O GCK3-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CCLK (I) TDO-I/O I/O GCK4-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ALL OTHERS
TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I)
TDI TCK TMS M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I)
TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (I) TDO
TDI TCK TMS M1 (LOW) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) CSO (I) DATA 4 (I) DATA 3 (I) RS (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (O) TDO WS (I) CS1 (I)
TDI TCK TMS M1 (HIGH) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT CCLK (I) TDO
DIN (I) DOUT CCLK (I) TDO
DIN (I) DOUT CCLK (O) TDO
CS1 (I)
Notes: 1. A shaded table cell represents a 20-k to 100-k pull-up resistor before and during configuration. 2. (I) represents an input (O) represents an output. 3. INIT is an open-drain output during configuration.
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XC5200 Series Field Programmable Gate Arrays Configuration Switching Characteristics
Vcc T POR RE-PROGRAM >300 ns PROGRAM T PI INIT T ICCK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) X1532 I/O VALID DONE RESPONSE <300 ns TCCLK
Master Modes
Description Power-On-Reset Program Latency CCLK (output) Delay period (slow) period (fast) Symbol TPOR TPI TICCK TCCLK TCCLK Min 2 6 40 640 100 Max 15 70 375 3000 375 Units ms s per CLB column s ns ns
7
Slave and Peripheral Modes
Description Symbol Min Max Units 2 15 ms Power-On-Reset TPOR 6 70 s per CLB column Program Latency TPI 5 s CCLK (input) Delay (required) TICCK TCCLK 100 ns period (required) At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until Note:
VCC is valid.
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XC5200 Series Field Programmable Gate Arrays XC5200 Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reflect worst-case values over the recommended operating conditions.
Finished Internal Net
3 T RTL
rdbk.TRIG
T RTRC T RCRT 2
1
rdclk.I
4 T RCL T RCH 5
rdbk.RIP
6 T RCRR
rdbk.DATA
DUMMY
T RCRD
DUMMY
VALID
VALID
7 X1790
rdbk.TRIG rdclk.1
Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time
1 2 7 6 5 4
Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL
Min 200 50 250 250
Max 250 250 500 500
Units ns ns ns ns ns ns
Note 1: Timing parameters apply to all speed grades. Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback
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XC5200 Series Field Programmable Gate Arrays
XC5200 Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1 Advance:
XC5200 Operating Conditions
Symbol VCC VIHT VILT VIHC VILC TIN Description Supply voltage relative to GND Commercial: 0C to 85C junction Supply voltage relative to GND Industrial: -40C to 100C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns
XC5200 DC Characteristics Over Operating Conditions
Symbol VOH VOL ICCO IIL CIN IRIN
Note:
Description High-level output voltage @ IOH = -8.0 mA, VCC min Low-level output voltage @ IOL = 8.0 mA, VCC max Quiescent FPGA supply current (Note 1) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested)
Min 3.86
Max 0.4 15 +10 15 0.30
Units V V mA A pF mA
7
-10 0.02
1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a tie option.
XC5200 Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature in plastic packages Junction temperature in ceramic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
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XC5200 Series Field Programmable Gate Arrays XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Description Global Signal Distribution From pad through global buffer, to any clock (CK) Symbol TBUFG Device XC5202 XC5204 XC5206 XC5210 XC5215 -6 Max (ns) 9.1 9.3 9.4 9.4 10.5 -5 Max (ns) 8.5 8.7 8.8 8.8 9.9 -4 Max (ns) 8.0 8.2 8.3 8.5 9.8 -3 Max (ns) 6.9 7.6 7.7 7.7 9.6
XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Description TBUF driving a Longline TS I O TBUF I to Longline, while TS is Low; i.e., buffer is constantly active TS going Low to Longline going from floating High or Low to active Low or High Symbol TIO Device XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC52xx -6 Max (ns) 6.0 6.4 6.6 6.6 7.3 7.8 8.3 8.4 8.4 8.9 3.0 -5 Max (ns) 3.8 4.1 4.2 4.2 4.6 5.6 5.9 6.0 6.0 6.3 2.8 -4 Max (ns) 3.0 3.2 3.3 3.3 3.8 4.7 4.9 5.0 5.0 5.3 2.6 -3 Max (ns) 2.0 2.3 2.7 2.9 3.2 4.0 4.3 4.4 4.4 4.5 2.4
TON
TS going High to TBUF going inactive, not driving Longline
size.
TOFF
Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array
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XC5200 Series Field Programmable Gate Arrays XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Description Combinatorial Delays F inputs to X output F inputs via transparent latch to Q DI inputs to DO output (Logic-Cell Feedthrough) F inputs via F5_MUX to DO output Carry Delays Incremental delay per bit Carry-in overhead from DI Carry-in overhead from F Carry-out overhead to DO Sequential Delays Clock (CK) to out (Q) (Flip-Flop) Gate (Latch enable) going active to out (Q) Set-up Time Before Clock (CK) F inputs F inputs via F5_MUX DI input CE input Hold Times After Clock (CK) F inputs F inputs via F5_MUX DI input CE input Clock Widths Clock High Time Clock Low Time Toggle Frequency (MHz) (Note 3) Reset Delays Width (High) Delay from CLR to Q (Flip-Flop) Delay from CLR to Q (Latch) Global Reset Delays Width (High) Delay from internal GR to Q Symbol Min (ns) -6 Max (ns) 5.6 8.0 4.3 7.2 0.7 1.8 3.7 4.0 5.8 9.2 2.3 3.8 0.8 1.6 0 0 0 0 6.0 6.0 83 6.0 7.7 6.5 6.0 14.7 6.0 12.1 6.0 6.3 5.2 6.0 9.1 1.8 3.0 0.5 1.2 0 0 0 0 6.0 6.0 83 6.0 5.1 4.2 6.0 8.0 Min (ns) -5 Max (ns) 4.6 6.6 3.5 5.8 0.6 1.6 3.2 3.2 4.9 7.4 1.4 2.5 0.4 0.9 0 0 0 0 6.0 6.0 83 6.0 4.0 3.0 Min (ns) -4 Max (ns) 3.8 5.4 2.8 5.0 0.5 1.5 2.9 2.5 4.0 5.9 1.3 2.4 0.4 0.9 0 0 0 0 6.0 6.0 83 Min (ns) -3 Max (ns) 3.0 4.3 2.4 4.3 0.5 1.4 2.4 2.1 4.0 5.5
TILO TITO TIDO TIMO TCY TCYDI TCYL TCYO TCKO TGO TICK TMICK TDICK TEICK TCKI TCKMI TCKDI TCKEI TCH TCL FTOG TCLRW TCLR TCLRL TGCLRW TGCLR
7
Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die. 2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator. 3. Maximum flip-flop toggle rate for export control purposes.
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XC5200 Series Field Programmable Gate Arrays XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. Speed Grade Description Global Clock to Output Pad (fast)
BUFG
-6 Max (ns) 16.9 17.1 17.2 17.2 19.0 21.4 21.6 21.7 21.7 24.3 2.5 2.3 2.2 2.2 2.0 3.8 3.9 4.4 5.1 5.8 7.3 7.3 7.2 7.2 6.8 8.8 8.6 8.5 8.5 8.5 0
-5 Max (ns) 15.1 15.3 15.4 15.4 17.0 18.7 18.9 19.0 19.0 21.2 2.0 1.9 1.9 1.9 1.8 3.8 3.9 4.4 5.1 5.8 6.6 6.6 6.5 6.5 5.7 7.7 7.5 7.4 7.4 7.4 0
-4 Max (ns) 10.9 11.3 11.9 12.8 12.8 12.6 13.3 13.6 15.0 15.0 1.9 1.9 1.9 1.9 1.7 3.5 3.8 4.4 4.9 5.7 6.6 6.6 6.4 6.0 5.7 7.5 7.5 7.4 7.4 7.4 0
-3 Max (ns) 9.8 9.9 10.8 11.2 11.7 11.5 11.9 12.5 12.9 13.1 1.9 1.9 1.9 1.8 1.7 3.5 3.6 4.3 4.8 5.6 6.6 6.6 6.3 6.0 5.7 7.5 7.5 7.4 7.3 7.2 0
Symbol TICKOF . . . . (Max)
Device XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC52xx
CLB Q
Direct IOB Connect
FAST
Global Clock-to-Output Delay
Global Clock to Output Pad (slew-limited)
BUFG
TICKO . . . . (Max)
CLB Q
Direct IOB Connect
Global Clock-to-Output Delay
Input Set-up Time (no delay) to CLB Flip-Flop IOB(NODELAY) Direct CLB Connect Input F,DI Set-up
& Hold Time BUFG
TPSUF (Min)
Input Hold Time (no delay) to CLB Flip-Flop IOB(NODELAY) Direct CLB Connect Input F,DI Set-up
& Hold Time BUFG
TPHF (Min)
Input Set-up Time (with delay) to CLB Flip-Flop DI Input Direct IOB Connect CLB Input DI Set-up
& Hold Time BUFG
TPSU
Input Set-up Time (with delay) to CLB Flip-Flop F Input Direct IOB Connect CLB Input F Set-up
& Hold Time BUFG
TPSUL (Min)
Input Hold Time (with delay) to CLB Flip-Flop Direct IOB Connect CLB Input F,DI Set-up
& Hold Time BUFG
TPH (Min)
Note: 1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG
properties, or XACT-Performance, can be used to assure that direct connects are used. tPSU applies only to the CLB input DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. tPSUL applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB Q outputs. 2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
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XC5200 Series Field Programmable Gate Arrays XC5200 IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used in the simulator. Speed Grade Description Input Propagation Delays from CMOS or TTL Levels Pad to I (no delay) Pad to I (with delay) Output Propagation Delays to CMOS or TTL Levels Output (O) to Pad (fast) Output (O) to Pad (slew-limited) From clock (CK) to output pad (fast), using direct connect between Q and output (O) From clock (CK) to output pad (slew-limited), using direct connect between Q and output (O) 3-state to Pad active (fast) 3-state to Pad active (slew-limited) Internal GTS to Pad active Symbol -6 Max (ns) -5 Max (ns) -4 Max (ns) -3 Max (ns)
TPI TPID
5.7 11.4
5.0 10.2
4.8 10.2
3.3 9.5
TOPF TOPS TOKPOF TOKPOS TTSONF TTSONS TGTS
4.6 9.5 10.1 14.9 5.6 10.4 17.7
4.5 8.4 9.3 13.1 5.2 9.0 15.9
4.5 8.0 8.3 11.8 4.9 8.3 14.7
3.5 5.0 7.5 10.0 4.6 6.0 13.5
7
Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. 2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors. 3. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
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XC5200 Series Field Programmable Gate Arrays XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC5200 devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold TTDITCK Input (TDI) to clock (TCK) setup time TTCKTDI Input (TDI) to clock (TCK) hold time TTMSTCK Input (TMS) to clock (TCK) setup time TTCKTMS Input (TMS) to clock (TCK) hold time Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH TTCKL Clock (TCK) Low FMAX (MHz) FMAX
Note 1:
-6 Min 30.0 0 15.0 0 Max Min 30.0 0 15.0 0
-5 Max Min 30.0 0 15.0 0
-4 Max Min 30.0 0 15.0 0
-3 Max
30.0 30.0 30.0 10.0 30.0 30.0
30.0 30.0 30.0 10.0
30.0 30.0 30.0 10.0
30.0
10.0
Input pad setup and hold times are specified with respect to the internal clock.
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XC5200 Series Field Programmable Gate Arrays
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die, and include boundary scan register locations.
Pin Locations for XC5202 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information. Pin
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
Description
VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) GND I/O (A12) I/O (A13) I/O (A14) I/O (A15) VCC GND
VQ64*
57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10
PC84
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -
PQ100
92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VQ100
89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
TQ144
128 129 130 131 132 133 134 137 138 139 142 143 144 1 2 3 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 32 33 34 35 36 37 38 39
PG156
H3 H1 G1 G2 G3 F1 F2 F3 E3 C1 B1 B2 C3 C4 B3 A1 B4 A3 C6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 C11 B12 A13 B13 B14 A15 C13 A16 C14 B15 B16
Boundary Scan Order
51 54 57 63 66 69 78 81 90 93 102 105 111 114 117 123 126 129 135 138 141 147 150 153 159 162 165 171 174 177 186 189 192 195
11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
GCK1 (A16, I/O) I/O (A17) I/O (TDI) I/O (TCK) GND I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O)
7
21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34.
11 12 13 14 15 16 17 18
25 26 27 28 29 30 31 32 33 34 35
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XC5200 Series Field Programmable Gate Arrays
Pin
35. 36. 37. 38. 39. 40. 41. 42. 43.
Description
I/O (HDC) I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND
VQ64*
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
PC84
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PQ100
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
VQ100
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
TQ144
40 43 44 45 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 65 66 69 70 71 72 73 74 75 76 79 80 81 84 85 86 87 88 89 90 91 92 93 94 95 96 97 100 101 102 105 106
PG156
D14 E14 C16 F14 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 L14 P16 M14 N14 R16 P14 R15 P13 R14 T16 T15 T14 T13 P11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 P6 T3 P5 P4 T2
Boundary Scan Order
204 207 210 216 219 222 228 231 234 240 243 246 252 255 258 264 267 276 279 288 291 300 303 306 312 315 318 324 327 336 339 342 348 351 360 363 366 372 375
44. 45. 46. 47. 48. 49. 50. 51. 52. 53.
I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O (D6) I/O GND I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O GND I/O (D1) I/O (RCLK-BUSY/RDY) I/O (D0, DIN) I/O (DOUT)
54. 55. 56. 57. 58. 59. 60. 61. 62. 63.
64. 65. 66. 67. 68. 69. 70. 71. 72. 73.
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XC5200 Series Field Programmable Gate Arrays
Pin Description
CCLK VCC 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O (A2, CS1) I/O (A3) GND I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND
VQ64*
48 49 50 51 52 53 54 55 56
PC84
73 74 75 76 77 78 79 80 81 82 83 84 1
PQ100
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
VQ100
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
TQ144
107 108 109 110 111 112 115 116 118 121 122 123 124 125 126 127
PG156
R2 P3 T1 N3 R1 P2 P1 N1 L3 K3 K2 K1 J1 J2 J3 H2
Boundary Scan Order
0 9 15 18 21 27 30 33 39 42 45 -
* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
Additional No Connect (N.C.) Connections on TQ144 Package
TQ144 135 136 140 141 4 5 9 10 25 26 30 31 41 42 46 47 62 63 67 68 77 78 82 83 98 99 103 104 113 114 117 119 120
7
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD
Pin Locations for XC5204 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Description VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O PC84 2 3 4 5 6 7 8 PQ100 92 93 94 95 96 97 98 99 100 VQ100 89 90 91 92 93 94 95 96 97 TQ144 128 129 130 131 132 133 134 135 136 137 138 139 140 PG156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 PQ160 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Boundary Scan Order 78 81 87 90 93 99 102 105 111 114 117 123 126
November 5, 1998 (Version 5.2)
7-135
R
XC5200 Series Field Programmable Gate Arrays
Pin 14. 15. 16. Description I/O I/O (A14) I/O (A15) VCC GND 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O GND VCC 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O PC84 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PQ100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 VQ100 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQ144 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PG156 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15 PQ160 157 158 159 160 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Boundary Scan Order 129 138 141 150 153 159 162 165 171 174 177 180 183 186 189 195 198 201 207 210 213 219 222 225 231 234 237 240 243 246 249 258 261 264 267 276 279 282 288 291 294 300 303
7-136
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 57. 58. 59. 60. 61. 62. 63. I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC 94. 95. 96. 97. 98. GND I/O (D3) I/O (RS) I/O I/O I/O (D2) Description PC84 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 PQ100 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 VQ100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 TQ144 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PG156 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 PQ160 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Boundary Scan Order 306 312 315 318 324 327 330 336 339 348 351 354 360 363 366 372 375 378 384 387 390 396 399 408 411 420 423 426 432 435 438 444 447 450 456 459 462 468 471 474 480 483
7
November 5, 1998 (Version 5.2)
7-137
R
XC5200 Series Field Programmable Gate Arrays
Pin 99. 100. 101. 102. 103. 104. 105. 106. 107. I/O I/O I/O GND I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND Description PC84 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 PQ100 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 VQ100 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 TQ144 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 PG156 T5 R6 T4 P6 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 PQ160 107 108 109 110 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 137 138 139 140 141 Boundary Scan Order 486 492 495 498 504 507 510 516 519 0 9 15 18 21 27 30 33 39 42 45 51 54 57 63 66 69 -
Additional No Connect (N.C.) Connections for PQ160 Package
8 9 30 31 PQ160 89 90 111 112 136
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD
7-138
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays Pin Locations for XC5206 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Description VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O (A15) VCC GND 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O I/O I/O GND VCC 37. 38. 39. 40. 41. I/O I/O I/O I/O I/O PC84 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PQ100 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VQ100 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TQ144 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PQ160 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TQ176 155 156 157 158 159 160 161 162 163 164 165 166 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PG191 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 PQ208 183 184 185 186 187 188 189 190 191 192 193 194 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Boundary Scan Order 87 90 93 99 102 105 111 114 117 123 126 129 138 141 150 153 162 165 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 246 249 255 258 261 267 270
7
November 5, 1998 (Version 5.2)
7-139
R
XC5200 Series Field Programmable Gate Arrays
Pin 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. Description I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O PC84 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 PQ100 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 VQ100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 TQ144 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PQ160 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 TQ176 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 PG191 C11 B11 A12 B12 A13 C12 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 T18 PQ208 32 33 34 35 36 37 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62 63 64 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 93 Boundary Scan Order 273 279 282 285 291 294 297 303 306 309 315 318 321 330 333 336 339 348 351 354 360 363 372 375 378 384 387 390 396 399 402 408 411 414 420 423 426 432 435 438 444 447 450 456 459
7-140
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 87. 88. 89. 90. 91. 92. 93. Description I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK-BUSY/RD Y) I/O I/O I/O (D0, DIN) I/O (DOUT) PC84 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 PQ100 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VQ100 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 TQ144 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 PQ160 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 TQ176 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PG191 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 U5 T6 V3 V2 PQ208 94 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 145 146 147 148 Boundary Scan Order 468 471 480 483 486 492 495 504 507 516 519 522 528 531 534 540 543 552 555 558 564 567 570 576 579 588 591 600 603 612 615 618 624 627 630 636 639 642 648
7
126. 127. 128. 129.
71 72
75 76
72 73
103 104 105 106
115 116 117 118
127 128 129 130
U4 T5 U3 T4
149 150 151 152
651 654 660 663
November 5, 1998 (Version 5.2)
7-141
R
XC5200 Series Field Programmable Gate Arrays
Pin Description CCLK VCC 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148. I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND PC84 73 74 75 76 77 78 79 80 81 82 83 84 1 PQ100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 VQ100 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 TQ144 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 PQ160 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 TQ176 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 PG191 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 M3 P1 N1 M2 M1 L3 L2 L1 K1 K2 K3 K4 PQ208 153 154 159 160 161 162 163 164 165 166 167 168 171 172 173 174 175 176 177 178 179 180 181 182 Boundary Scan Order 9 15 18 21 27 30 33 42 45 51 54 57 63 66 69 75 78 81 -
Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages
195 196 206 207 208 1 3 12 13 38 39 51 52 53 54 PQ208 65 66 91 92 102 104 105 107 117 118 143 144 155 156 157 158 169 170 TQ176 167
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD
Pin Locations for XC5210 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin VCC 1. 2. 3. 4. 5. 6. I/O (A8) I/O (A9) I/O I/O I/O I/O Description PC84 2 3 4 TQ144 128 129 130 131 132 PQ160 142 143 144 145 146 TQ176 155 156 157 158 159 160 161 PQ208 183 184 185 186 187 188 189 PG223 J4 J3 J2 J1 H1 H2 H3 BG225 VCC* E8 B7 A7 C7 D7 E7 PQ240 212 213 214 215 216 217 218 Boundary Scan Order 111 114 117 123 126 129
7-142
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Description I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O (A15) VCC 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC 49. I/O PC84 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TQ144 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PQ160 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TQ176 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PQ208 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PG223 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 BG225 A6 B6 VCC* C6 F7 A5 B5 GND* D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC* GND* D4 B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND* F5 E1 F4 F3 VCC* F2 F1 G4 G3 G2 G1 G5 H3 GND* VCC* H4 PQ240 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 Boundary Scan Order 135 138 141 150 153 162 165 171 174 177 183 186 189 195 198 201 210 213 222 225 231 234 237 243 246 249 255 258 261 267 270 273 279 282 285 291 294 297 306 309 318 321 327
7
November 5, 1998 (Version 5.2)
7-143
R
XC5200 Series Field Programmable Gate Arrays
Pin 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O Description PC84 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 TQ144 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 PQ160 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 TQ176 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 PQ208 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 PG223 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15 BG225 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND* P2 VCC* M4 R2 P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 PQ240 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 Boundary Scan Order 330 333 339 342 345 351 354 357 363 366 369 375 378 381 387 390 393 399 402 405 411 414 417 426 429 432 435 444 447 450 456 459 462 468 471 474 480 483 486 492 495 504 507 510 516
7-144
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 95. 96. 97. 98. 99. I/O I/O I/O I/O I/O (ERR, INIT) VCC GND 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O Description PC84 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 TQ144 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 PQ160 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 TQ176 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 PQ208 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 117 118 119 PG223 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 BG225 P7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 R10 P10 VCC* N10 K9 R11 P11 GND* M10 N11 R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 GND* P14 VCC* M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND* L15 PQ240 85 86 87 88 89 90 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Boundary Scan Order 519 522 528 531 534 540 543 546 552 555 558 564 567 570 576 579 588 591 600 603 606 612 615 618 624 627 630 636 639 648 651 660 663 666 672 675 678 684 687 690 696 699
7
November 5, 1998 (Version 5.2)
7-145
R
XC5200 Series Field Programmable Gate Arrays
Pin 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC 172. 173. 174. 175. 176. 177. 178. 179. I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (CS1, A2) I/O (A3) I/O Description PC84 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TQ144 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 PQ160 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TQ176 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 PQ208 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 159 160 161 162 163 164 165 166 PG223 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P4 BG225 K12 K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12 G11 F15 VCC* F14 F13 G10 E15 GND* E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC* A15 GND* A14 B13 E11 C12 A13 B12 F9 PQ240 137 138 139 140 141 142 144 145 146 147 148 149 150 151 152 153 154 155 156 157 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Boundary Scan Order 708 711 714 720 723 726 732 735 738 744 747 756 759 768 771 780 783 786 792 795 798 804 807 810 816 819 822 828 831 834 840 843 846 855 858 9 15 18 21 27 30 33
7-146
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 180. 181. 182. 183. 184. I/O I/O I/O I/O I/O GND 185. 186. 187. 188. 189. 190. 191. 192. 193. 194. 195. 196. I/O I/O I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND Description PC84 81 82 83 84 1 TQ144 117 118 119 120 121 122 123 124 125 126 127 PQ160 129 130 131 132 133 134 135 136 137 138 139 140 141 TQ176 141 142 143 144 145 146 147 148 149 150 151 152 153 154 PQ208 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 PG223 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 BG225 D11 A12 C11 B11 E10 GND* A11 D10 C10 B10 VCC* A10 D9 C9 B9 A9 E9 C8 B8 GND* PQ240 190 191 192 193 194 196 197 198 199 200 201 202 203 205 206 207 208 209 210 211 Boundary Scan Order 39 42 45 51 54 57 66 69 75 78 81 87 90 93 99 102 105 -
Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages
1 3 51 52 53 54 102 104 PQ208 105 107 155 156 157 158 206 207 208 22 37 83 98 PQ240 143 158 195 204 219
7
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, D8, H15, R8,
B14, R1, H1, and R15. Pins labeled GND* are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD
Pin Locations for XC5215 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin VCC 1. 2. 3. 4. 5. 6. 7. I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) Description PQ160 142 143 144 145 146 147 HQ208 183 184 185 186 187 188 189 190 HQ240 212 213 214 215 216 217 218 220 PG299 K1 K2 K3 K5 K4 J1 J2 H1 BG225 VCC* E8 B7 A7 C7 D7 E7 A6 BG352 VCC* D14 C14 A15 B15 C15 D15 A16 Boundary Scan Order 138 141 147 150 153 159 162
November 5, 1998 (Version 5.2)
7-147
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XC5200 Series Field Programmable Gate Arrays
Pin 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. Description I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O PQ160 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HQ208 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 HQ240 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PG299 J3 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 C2 F5 E4 D3 C3 A2 B1 D4 B2 B3 E6 D5 C4 A3 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 E9 B8 BG225 B6 VCC* C6 F7 A5 B5 GND* D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC* GND* D4 B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND* F5 E1 F4 F3 VCC* F2 F1 BG352 B16 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 D20 A23 D21 C22 B24 C23 D22 C24 VCC* GND* D23 C25 D24 E23 C26 E24 F24 E25 D26 G24 F25 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* L24 K25 L25 Boundary Scan Order 165 171 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 243 246 249 258 261 270 273 279 282 285 294 297 303 306 309 315 318 321 327 330 333 339 342 345 351 354 357 363
7-148
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 54. 55. 56. 57. 58. 59. 60. I/O I/O I/O I/O I/O I/O I/O GND 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) Description PQ160 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 HQ208 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 56 57 58 59 60 61 62 HQ240 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PG299 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 E12 B13 A16 A14 C13 B14 D13 A15 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 A20 A19 C18 B20 D17 B19 C19 F16 E17 D18 C20 BG225 G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND* P2 VCC* M4 R2 P3 L5 N4 R3 P4 BG352 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC* AC23 AE24 AD23 AC22 AF24 AD22 AE23 Boundary Scan Order 366 369 375 378 381 390 393 399 402 405 411 414 417 423 426 429 435 438 441 447 450 453 459 462 465 471 474 477 483 486 489 495 498 501 507 510 513 522 525 528 531 540 543 546 552 555
7
November 5, 1998 (Version 5.2)
7-149
R
XC5200 Series Field Programmable Gate Arrays
Pin 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O Description PQ160 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 HQ208 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 HQ240 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 107 108 109 110 111 112 PG299 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 F20 J16 G20 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19 N20 M18 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20 BG225 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 P7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 R10 P10 VCC* N10 K9 R11 P11 GND* M10 N11 R12 L10 P12 M11 BG352 AE22 AF23 AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE17 AE16 AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AD11 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 Boundary Scan Order 558 564 567 570 576 579 582 588 591 594 600 603 606 612 615 618 624 627 630 636 639 642 648 651 660 663 672 675 678 684 687 690 696 699 702 708 711 714 720 723 726 732 735 738 744 747
7-150
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 146. 147. 148. 149. 150. 151. 152. 153. I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. 180. 181. 182. 183. PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND 184. 185. 186. 187. 188. 189. I/O (D3) I/O (RS) I/O I/O I/O I/O Description PQ160 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 HQ208 95 96 97 98 99 100 101 103 106 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 HQ240 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 144 145 146 147 148 149 150 151 152 153 154 155 156 157 PG299 R17 T18 U19 V19 R16 T17 U18 X20 W20 V18 X19 U17 W19 W18 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 X13 V12 W12 T11 X12 U11 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9 BG225 R13 N12 P13 K10 R14 N13 GND* P14 VCC* M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND* L15 K12 K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12 BG352 AD6 AC7 AF4 AF3 AD5 AE3 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AA4 AA3 AB2 AC1 Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 Boundary Scan Order 750 756 759 768 771 774 780 783 792 795 804 807 810 816 819 828 831 834 840 843 846 852 855 858 864 867 870 876 879 882 888 891 894 900 903 906 912 915 924 927 936 939 942 948
7
November 5, 1998 (Version 5.2)
7-151
R
XC5200 Series Field Programmable Gate Arrays
Pin 190. 191. 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. 208. 209. 210. 211. 212. 213. I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234. VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC Description PQ160 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 HQ208 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 HQ240 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 PG299 X8 V9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 W4 W3 T6 U5 V4 X1 V3 W1 U4 X2 W2 V2 R5 T4 U3 V1 R4 P5 U2 T3 U1 P4 R3 N5 T2 R2 T1 N4 P3 P2 N3 R1 BG225 G11 F15 VCC* F14 F13 G10 E15 GND* E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC* A15 GND* A14 B13 E11 C12 A13 B12 F9 D11 A12 C11 B11 E10 GND* A11 D10 C10 B10 VCC* BG352 M4 L1 J1 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 F3 G4 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 D6 C6 B5 A4 C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* Boundary Scan Order 951 954 960 963 966 972 975 978 984 987 990 996 999 1002 1008 1011 1014 1020 1023 1032 1035 1038 1044 1047 0 9 15 18 21 27 30 33 39 42 45 51 54 57 63 66 69 75 78 81 87 -
7-152
November 5, 1998 (Version 5.2)
R
XC5200 Series Field Programmable Gate Arrays
Pin 235. 236. 237. 238. 239. 240. 241. 242. 243. 244. I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND Description PQ160 134 135 136 137 138 139 140 141 HQ208 174 175 176 177 178 179 180 181 182 HQ240 202 203 205 206 207 208 209 210 211 PG299 M5 P1 N1 M3 M2 L5 M1 L4 L3 L2 L1 BG225 A10 D9 C9 B9 A9 E9 C8 B8 GND* BG352 B11 A11 D12 C12 B12 A12 C13 B13 A13 B14 GND* Boundary Scan Order 90 93 99 102 105 111 114 117 126 129 -
Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages
HQ208 206 207 208 1 3 51 52 53 54 102 104 105 107 155 156 157 158 HQ240 219 22 37 83 98 143 158 204 -
7
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17. Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are: A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD
November 5, 1998 (Version 5.2)
7-153
R
XC5200 Series Field Programmable Gate Arrays
Product Availability
PINS 64 Plast. VQFP 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 144 Plast. TQFP 156 Ceram. PGA 160 Plast. PQFP 176 Plast. TQFP 191 Ceram. PGA 208 High-Perf. QFP 208 Plast. PQFP 223 Ceram. PGA 225 Plast. BGA 240 High-Perf. QFP 240 Plast. PQFP 299 Ceram. PGA 352 Plast. BGA BG352 244 TYPE
HQ208
HQ240
PQ100
VQ100
PG156
PQ160
PG191
PQ208
PG223
BG225
PQ240
PG299
CI C C C PG299 244
CODE
-6
CI CI C C
CI CI C C CI CI C C CI CI C C CI CI C C
CI CI C C CI CI C C CI CI C C
CI CI C C CI CI C C CI CI C C
CI CI C C CI CI C C CI CI C C CI CI C C
CI CI C C CI CI C C CI CI C C CI CI C C CI CI C C CI C C C CI CI C C CI CI C C CI C C C CI CI C C CI CI C C CI CI C C CI CI C C CI CI C C CI C C C CI C C C CI CI C C CI C C C
XC5202
-5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3 -6 -5 -4 -3
XC5204
XC5206
XC5210
XC5215
7/8/98
C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C * VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
User I/O Per Package
Device XC5202 XC5204 XC5206 XC5210 XC5215
7/8/98 Max I/O 84 124 148 196 244
Package Type
VQ64 52 PC84 65 65 65 65 PQ100 81 81 81 VQ100 81 81 81 TQ144 84 117 117 117 PG156 84 124 124 133 133 133 148 149 164 148 148 164 196 196 196 197 196 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240
Ordering Information
Example: Device Type Speed Grade
XC5210-6PQ208C
Temperature Range Number of Pins Package Type
7-154
November 5, 1998 (Version 5.2)
BG352
TQ144
TQ176
VQ64*
PC84
R
XC5200 Series Field Programmable Gate Arrays
Revisions
Version 12/97 7/98 11/98 Description Rev 5.0 added -3, -4 specification Rev 5.1 added Spartan family to comparison, removed HQ304 Rev 5.2 All specifications made final.
7
November 5, 1998 (Version 5.2)
7-155

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